Single fin structures

ABSTRACT

The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

FIELD OF THE INVENTION

The present disclosure generally relates to semiconductor structuresand, more particularly, to single fin structures and methods ofmanufacture.

BACKGROUND

As semiconductor processes continue to scale downwards, e.g., shrink,the desired spacing between features (i.e., the pitch) also becomessmaller. To this end, in the smaller technology nodes it becomes evermore difficult to fabricate features due to the critical dimension (CD)scaling and process capabilities.

Single fin structures are desirable for certain applications. However,single fin structures can suffer from crystal defects caused by stressfrom flowable chemical vapor deposition (FCVD) processes used to formshallow trench isolation (STI) structures. Specifically, stress from theFCVD process causes densification and shrinkage of the fin substrateduring thermal annealing, thereby pulling apart the fin structure andcausing leakage issues within the gate structures. Accordingly, thesecrystal defects can cause significant yield loss and malfunction forsingle fin structures.

SUMMARY

In an aspect of the disclosure, a structure comprises: an active singlefin structure; a plurality of dummy fin structures on opposing sides ofthe active single fin structure; source and drain regions formed on theactive single fin structure and the dummy fin structures; recessedshallow trench isolation (STI) regions between the dummy fin structuresand the active single fin structure and below a surface of the dummy finstructures; and contacts formed on the source and drain regions of theactive single fin structure with a spacing of at least two dummy finstructures on opposing sides of the contacts.

In an aspect of the disclosure, a structure comprises: a fin structurein an active region of a device; a plurality of fin structures ininactive regions of the device and on opposing sides of the finstructure in the active region; source and drain regions on the finstructures in both the active region and the inactive regions; recessedshallow trench isolation (STI) regions between fin structures in boththe active region and the inactive regions; and contacts formed on thesource and drain regions in the active region with a spacing of at leasttwo fin structures.

In an aspect of the disclosure, a method comprises: forming an activesingle fin structure; forming a plurality of dummy fin structures onopposing sides of the active single fin structure; forming source anddrain regions on the active single fin structure and the dummy finstructures; forming shallow trench isolation (STI) regions between thedummy fin structures and the active single fin structure and below asurface of the dummy fin structures; and forming contacts formed on thesource and drain regions of the active single fin structure with aspacing of at least two dummy fin structures on opposing sides of thecontacts.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is described in the detailed description whichfollows, in reference to the noted plurality of drawings by way ofnon-limiting examples of exemplary embodiments of the presentdisclosure.

FIGS. 1A and 1B show fin structures, amongst other features, andrespective fabrication processes in accordance with aspects of thepresent disclosure.

FIGS. 2A and 2B show an insulator material between the fin structures,amongst other features, and respective fabrication processes inaccordance with aspects of the present disclosure.

FIG. 3 shows a recessed insulator material between the fin structures,amongst other features, and respective fabrication processes inaccordance with aspects of the present disclosure.

FIGS. 4A and 4B show a dummy gate structure, amongst other features, andrespective fabrication processes in accordance with aspects of thepresent disclosure.

FIGS. 5A and 5B show source and drain regions, amongst other features,and respective fabrication processes in accordance with aspects of thepresent disclosure.

FIGS. 6A and 6B show a replacement gate structure, amongst otherfeatures, and respective fabrication processes in accordance withaspects of the present disclosure.

FIGS. 7A and 7B show source and drain contacts, amongst other features,and respective fabrication processes in accordance with aspects of thepresent disclosure.

FIG. 8 shows metallization features, amongst other features, andrespective fabrication processes in accordance with aspects of thepresent disclosure.

DETAILED DESCRIPTION

The present disclosure generally relates to semiconductor structuresand, more particularly, to single fin structures and methods ofmanufacture. In embodiments, the processes and structures providedherein allow for dummy fins to be formed adjacent to an active singlefin device, i.e., field effect transistor (finFET). Advantageously, byforming a plurality of dummy fins, degradation of a single active fincaused by stress from formation of shallow trench isolation (STI)regions is prevented, thereby improving yield and device performance forsingle fin structures. The processes and structures described hereinallow for a single fin structure which is free of crystal defects,enabling low power consumption applications without leakage issues.

The processes described herein include dummy and active gate finformation, e.g., self-aligned double patterned (SADP) or sidewall imagetransfer (SIT) fin formation, and a flowable chemical vapor deposition(FCVD) shallow trench fill. The fin structures which are not active,i.e., dummy fin structures, are maintained during the flowable process.Following the flowable process, a dummy gate structure can be formedover the dummy fin structures and the active fin structure. Source anddrain regions are formed by an epitaxial growth, followed by formationof replacement gate structures. In this way, a plurality of finstructures with a one (1) fin pitch array can be formed, with dummy finstructures being maintained and source and drain contacts beingpatterned to land only on the single active fin structure. Inembodiments, the structures and processes described herein can beapplied to 14 nm technologies, or smaller.

The structures of the present disclosure can be manufactured in a numberof ways using a number of different tools. In general, though, themethodologies and tools are used to form structures with dimensions inthe micrometer and nanometer scale. The methodologies, i.e.,technologies, employed to manufacture the structure of the presentdisclosure have been adopted from integrated circuit (IC) technology.For example, the structures are built on wafers and are realized infilms of material patterned by photolithographic processes on the top ofa wafer. In particular, the fabrication of the structure uses threebasic building blocks: (i) deposition of thin films of material on asubstrate, (ii) applying a patterned mask on top of the films byphotolithographic imaging, and (iii) etching the films selectively tothe mask.

FIG. 1A depicts a top view of a structure 100; whereas, FIG. 1B depictsthe structure 100 along a line Y-Y of FIG. 1A. Specifically, FIGS. 1Aand 1B show an incoming structure 100 and respective fabricationprocesses in accordance with aspects of the present disclosure. Inembodiments, the structure 100 includes fin structures 120 composed of asubstrate 110, with trenches 125 between the fin structures 120. As anexample, the substrate 110 may be composed of any suitable substratematerial including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs,InAs, InP, etc. In further embodiments, the substrate 110 is a bulksubstrate or a silicon-on-insulator (SOI) substrate, for example.

In one illustrative example, the fin structures 120 can have a pitch of48 nm. Further, active fin structures can be separated from dummy finstructures. The fin structures 120 can be fabricated using aself-aligned double patterned (SADP) technique or a sidewall imagetransfer (SIT) technique. In an example of a SIT technique, a mandrelmaterial, e.g., SiO₂, is deposited on the substrate 110 usingconventional chemical vapor deposition (CVD) processes. A resist isformed on the mandrel material and exposed to light to form a pattern(openings). A reactive ion etching is performed through the openings toform the mandrels. In embodiments, the mandrels can have differentwidths and/or spacing depending on the desired dimensions of the finstructures 120. The mandrels are then covered with a deposition layer,which is etched to form spacers on the sidewalls of the mandrels whichare preferably material that is different than the mandrels, and whichare formed using conventional deposition processes known to those ofskill in the art. The spacers can have a width which matches thedimensions of the fin structures, for example. The mandrels are removedor stripped using a conventional etching process, selective to themandrel material. An etching is then performed within the spacing of thespacers to form the sub-lithographic features, e.g., fin structures 120.The sidewall spacers can then be stripped. In embodiments, the width ofeach fin structure can be different dimensions depending on the designparameters.

FIG. 2A depicts a top view of the structure 100 with insulator (e.g.,oxide) material between the fin structures 120; whereas, FIG. 2B depictsthe structure 100 along a line Y-Y of FIG. 2A. Specifically, FIGS. 2Aand 2B show the deposition of an oxide material within the trenches 125to form shallow trench isolation (STI) regions 130 between the finstructures 120, and specifically dummy fin structures 120 a over anon-device region and a single active fin structure 120 b over a deviceregion. The oxide material of the STI regions 130 can be deposited by aflowable chemical vapor deposition (FCVD) process in the trenches 125,followed by a CMP process to a top surface of the fin structures 120 toremove any excess material. In embodiments, the fin structure in theactive region, i.e., single active fin structure 120 b, and the finstructures, i.e., dummy fin structures 120 a, are composed of a samematerial, i.e., substrate 110.

The dummy fin structures 120 a do not have any contacts or metallizationfeatures connected thereto, while the single active fin structure 120 bis over an active region of the device and will have contacts andinterconnection structures extending therefrom. In further embodiments,the dummy fin structures 120 a are separated from one another by atleast 40 nm. in this way, the processes described herein include dummyfin structures 120 a which are formed to be separated from one anotherby at least 40 nm, and the spacing of the at least two dummy finstructures 120 a is formed by having the contacts land only on thesource and drain regions of the active single fin structure 120 b. Asillustrated in FIG. 2A, the dummy fin structures 120 a sit beside thesingle active fin structure 120 b. Specifically, the fin structure 120in the active region is a single fin structure 120 b surrounded by dummyfin structures 120 a.

FIG. 3 shows a recess process to form STI regions 130 in accordance withaspects of the present disclosure. In embodiments, the oxide is recessedto form one or more recesses 140 between the fin structures 120, whichalso exposes upper sidewalls of the fin structures 120. To recess theoxide of the STI regions 130, a selective chemistry with a timed etchingprocess will be used to form one or more recesses 140 of the oxidematerial of the STI regions 130. This will expose an upper portion ofthe fins 120. In embodiments, the recess process can be a masklessprocess. In this way, the STI regions 130 are recessed STI regions.Further, these recessed STI regions are composed of an oxide of aflowable chemical vapor deposition (FCVD).

In known processes, select fin structures (dummy fin structures 120 a)of the fin structures 120 are removed to form a deep STI structure;however, in the present disclosure, the dummy fin structures 120 a arenot removed and, instead, the dummy fin structures 120 a are maintainedto provide support to the single active fin structure 120 b.Accordingly, any stress on the substrate 110, and specifically thesingle active fin structure 120 b, caused by FCVD processes is reducedby the dummy fin structures 120 a. A reduction in the stress on thesingle active fin structure 120 b prevents crystal defects in thesubstrate 110, which allows for a reduction in leakage issues, yieldloss and malfunction. In further embodiments, the dummy fin structures120 a can be removed in later processing steps.

FIG. 4A depicts a top view of the structure 100 with a dummy gatestructure; whereas, FIG. 4B depicts the structure 100 along a line Y-Yof FIG. 4A. Specifically, FIGS. 4A and 4B show a dummy gate structure150 formed over the fin structures 120. In embodiments, the dummy gatestructure 150 is composed of a poly silicon (poly-Si) material, and isdeposited by conventional processes, e.g., chemical vapor deposition(CVD). In more specific embodiments, the dummy gate structure 150includes a deposition of a poly material, followed by a patterningprocess. Sidewall spacers can be formed on the sidewalls of thepatterned poly material using conventional deposition and anisotropicetching methods known to those of skill in the art such that no furtherexplanation is required for a complete understanding of the disclosure.In embodiments, a dielectric material can be deposited under the polymaterial. The dielectric material can be a high-k dielectric material asdescribed herein.

FIG. 5A depicts a top view of the structure 100 with source and drainregions; whereas, FIG. 5B depict the structure 100 along a line Y-Y ofFIG. 5A. Specifically, FIGS. 5A and 5B show source and drain regions(S/D) regions 160 formed on the fin structures 120 at sides of the dummygate structure 150 using, e.g., any conventional method. In thisexample, the S/D regions 160 can be raised S/D regions 160 formed by adoped epitaxial growth process on the surfaces of the fin structures120. As illustrated in FIG. 5B, the recessed STI regions 130 are below asurface of source and drain regions 160 on the dummy fin structures 120a. Specifically, the recessed STI regions 130 are below a bottom surfaceof the source and drain regions 160 on the dummy fin structures 120 a.

FIG. 6A depicts a top view of the structure 100 with a replacement gatestructure 170; whereas, FIG. 6B depicts the structure 100 along a lineY-Y of FIG. 6A. Specifically, FIGS. 6A and 6B illustrate removal of thedummy gate structure 150 and formation of the replacement gate structure170, along with the dummy fin structures 120 a and the single active finstructure 120 b. In embodiments, the dummy gate material of the dummygate structure 150, e.g., poly material, can be removed by a masklessetching process, e.g., a wet etch or dry etch process, due to itsselectivity with respect to the semiconductor material of the substrate110. In this way, the fin structure, i.e., single active fin structure120 b, in the active region includes an active gate structure.

The gate metal can be composed of any suitable conductive material bedeposited between sidewall spacers. For example, the gate material canbe different workfunction materials. Examples of the workfunctionmaterials for a p-channel FET include Ti, TiAlC, Al, TiAl, TaN, TaAlC,TiN, TiC and Co. In one embodiment, TiN is used for a p-channel FET.Examples of the workfunction materials for an n-channel FET include TiN,TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC. Inone embodiment, TaAlC, TiAl or Al is used for an n-channel FET. Theworkfunction materials may be formed by chemical vapor deposition (CVD),physical vapor deposition (PVD) including sputtering, atomic layerdeposition (ALD) or other suitable method. In embodiments, prior to thegate metal deposition, a gate dielectric material can be deposited by anatomic layer deposition (ALD) process, for example. The gate dielectricmaterial can be a high-k dielectric, e.g., HF₂O₂. Gate materials aredeposited over the gate dielectric.

FIG. 7A depicts a top view of the structure 100 with source/draincontacts; whereas, FIG. 7B depicts the structure 100 along a line Y-Y ofFIG. 7A. Specifically, FIGS. 7A and 7B illustrate the formation oftrench silicide (TS) structures 180 on the single active fin structure120 b, while the TS structures 180 are not formed over dummy finstructures 120 a. In this way, the contacts (TS structures 180) landonly on the active single fin structure 120 b.

Compared to known devices, the TS structures 180 of the presentdisclosure are smaller in overall size. Specifically, known devices havethe dummy fin structures 120 a removed, thereby providing greater spaceand direction for the TS structure formation. In comparison, thestructures described herein have the TS structures 180 limited by thedummy fin structures 120 a, which are not removed. In embodiments, theS/D regions 160 of dummy fin structures 120 a are covered by a maskingmaterial, while the S/D regions 160 of the single active fin structure120 b is left exposed.

A silicide liner is deposited over the S/D regions 160 of the singleactive fin structure 120 b and then subjected to a silicide process. Thesilicide liner can be deposited using physical vapor deposition (PVD) orCVD processes. In embodiments, the silicide liner can be Ti, Ni, NiPtand Co, amongst other examples. As should be understood by those ofskill in the art, the silicide process begins with deposition of a thintransition metal layer, e.g., nickel, cobalt or titanium, over fullyformed and patterned semiconductor devices (e.g., source and drainregions and respective devices). After deposition of the material, thestructure is heated allowing the transition metal to react with exposedsilicon (or other semiconductor material as described herein) in theactive regions of the semiconductor device (e.g., source, drain, gatecontact region) forming a low-resistance transition metal silicide.Following the reaction, any remaining transition metal is removed bychemical etching, leaving silicide contacts in the active regions of thedevice. It should be understood by those of skill in the art thatsilicide contacts will not be required on the devices, when a gatestructure is composed of a metal material.

Following the silicide process, a metal material is deposited on thesilicide liner, thereby forming the TS structures 180. In embodiments,the metal material can be composed of cobalt (Co) or tungsten (W) orRuthenium (Ru), for example. In further embodiments, a thin metal linermaterial can be deposited before deposition metal of the metal material,e.g. TiN, TaN. The deposition of the metal material is followed by a CMPpolishing process.

FIG. 8 illustrates the source and drain (S/D) contacts 200. In this way,the present disclosure provides for a structure which includes a finstructure (single active fin structure 120 b) in an active region of adevice (structure 100), and a plurality of fin structures (dummy finstructures 120 a) in inactive regions of the device and on opposingsides of the fin structure in the active region. Further, source anddrain regions 160 on the fin structures 120 a, 120 b in both the activeregion and the inactive regions. Additionally, recessed shallow trenchisolation (STI) regions 130 are between fin structures 120 a, 120 b inboth the active region and the inactive regions, with contacts 200formed on the source and drain regions 160 in the active region with aspacing of at least two fin structures (dummy fin structures 120 a).

In embodiments, an interlevel dielectric material (ILD) 190, e.g.,oxide) is deposited over the TS structures 180. The ILD 190 can becomprised of any suitable dielectric material, e.g., oxide, deposited bya CVD process. The ILD layer 190 is patterned using conventionallithography and etching processes to form one or more trenches in theILD 190, exposing the TS structures 180. A metal material is depositedwithin the trenches to form the S/D contacts 200. As illustrated in FIG.8 , the recessed STI regions 130 are below a bottom surface of thecontacts 200. Further, the contacts 200 are aligned with respect to amidpoint between at least two fin structures, i.e., dummy fin structures120 a, over the non-device regions. Additionally, the contacts 200 landonly on the fin structures, i.e., single active fin structure 120 b,which are in the active region.

In embodiments, the metal material can be deposited by CVD processes,and can be any suitable conductive material. For example, the metalmaterial can be tungsten (W), cobalt (Co) or copper (Cu), amongst otherexamples. The deposition of the metal material is followed by a CMPprocess. In this way, the structures and processes described hereinprovide for a structure having an active single fin structure 120 b, anda plurality of dummy fin structures 120 a on opposing sides of theactive single fin structure 120 b. Further, source and drain regions 160formed on the active single fin structure 120 b and the dummy finstructures 120 a, and recessed shallow trench isolation (STI) regions130 are between the dummy fin structures 120 a and the active single finstructure 120 b and below a surface of the dummy fin structures 120 a.Additionally, contacts, i.e., TS structures 180, are formed on thesource and drain regions 160 of the active single fin structure 120 bwith a spacing of at least two dummy fin structures 120 a on opposingsides of the contacts.

The method(s) as described above is used in the fabrication ofintegrated circuit chips. The resulting integrated circuit chips can bedistributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present disclosurehave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed:
 1. A structure, comprising: an active single finstructure; and a first plurality of dummy fin structures being directlyadjacent one side of the active single fin structure; a second pluralityof dummy fin structures being directly adjacent an opposing side of theactive single fin structure; and a space between the active single finstructure and the first and second plurality of dummy fin structuresbeing devoid of additional active fin structures.
 2. The structure ofclaim 1, wherein the first and second plurality of dummy fin structuresare over a non-device region, and the active single fin structure isover a device region.
 3. The structure of claim 1, further comprising:source and drain regions formed on the active single fin structure andon the first plurality of dummy fin structures and on the secondplurality of dummy fin structures; recessed shallow trench isolation(STI) regions between the first and second plurality of dummy finstructures and the active single fin structure and below a surface ofthe first and second plurality of dummy fin structures; and contactsformed on the source and drain regions of the active single finstructure with a spacing of the first plurality of dummy fin structureson one side of the contacts and the second plurality of dummy finstructures on an opposing side of the contacts, wherein the recessed STIregions are below a surface of the source and drain regions on the firstand second plurality of dummy fin structures.
 4. The structure of claim3, wherein the recessed STI regions are below a bottom surface of thesource and drain regions on the first and second plurality of dummy finstructures.
 5. The structure of claim 3, wherein the recessed STIregions are composed of an oxide of a flowable chemical vapor deposition(FCVD), the active single fin structure is over a device region, thefirst and second plurality of dummy fin structures are over a non-deviceregion, the recessed STI regions are below a bottom surface of thesource and drain regions on the first and second plurality of dummy finstructures, and the contacts land only on the active single finstructure.
 6. The structure of claim 3, wherein the contacts land onlyon the active single fin structure.
 7. The structure of claim 3, whereinthe contacts land only on the source and drain regions of the activesingle fin structure.
 8. The structure of claim 7, further comprising atrench silicide structure over the source and drain regions of theactive single fin structure.
 9. The structure of claim 8, furthercomprising an interlevel dielectric material over the trench silicidestructure.
 10. The structure of claim 1, wherein the first and secondplurality of dummy fin structures are separated from one another by atleast 40 nm.
 11. A structure, comprising: a fin structure in an activeregion of a device; a plurality of fin structures in inactive regions ofthe device and located directly adjacent the fin structure in the activeregion on opposing sides of the fin structure in the active region;source and drain regions on the fin structures in both the active regionand the inactive regions; recessed shallow trench isolation (STI)regions between the fin structures in both the active region and theinactive regions; and contacts formed on the source and drain regions inthe active region with a spacing of at least two fin structures, whereinthe recessed STI regions comprise oxide.
 12. The structure of claim 11,wherein the recessed STI regions are below a bottom surface of thecontacts.
 13. The structure of claim 11, wherein the recessed STIregions are below a surface of the fin structure in the active region.14. The structure of claim 11, wherein the inactive regions arenon-device regions.
 15. The structure of claim 14, wherein the contactsare aligned with respect to a midpoint between at least two finstructures over the non-device regions.
 16. The structure of claim 15,wherein the contacts land only on the fin structures which are in theactive region.
 17. The structure of claim 16, wherein the fin structurein the active region is a single fin structure surrounded by dummy finstructures.
 18. The structure of claim 17, wherein the fin structure inthe active region includes an active gate structure.
 19. The structureof claim 11, wherein the fin structure in the active region and the finstructures in the inactive regions are composed of a same material.